The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs. In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.
As semiconductor device sizes continue to shrink, it has become increasingly more difficult to meet device planarization requirements in fabrication. Conventional planarization methods typically involve performing a chemical-mechanical-polishing (CMP) process on a semiconductor wafer. However, these traditional planarization methods have not been able to achieve satisfactory performance for newer technology nodes such as the 15 nanometer (nm) technology node and beyond. As an example, the performance of existing planarization methods tend to suffer from planarization non-uniformity problems when the wafer has regions with different pattern densities.
Therefore, while existing semiconductor device planarization methods have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.